A System-on-Chip solution for a low power active capsule endoscope with therapeutic capabilities for clip application in the gastrointestinal tract

This paper addresses the circuit implementation challenges resulting from the integration of a therapeutic clip in a magnetically maneuverable wireless capsule intended for colonoscopy. To deal with the size constraints typical of a capsule endoscope, an Application Specific Integrated Circuit (ASIC) has been designed specifically to habilitate the release of the therapeutic clip. The ASIC is a complete System on Chip (SoC) that incorporates a circuit for the low power release of the clip, thus overcoming the limitations of the power supply system. With a size of 14mm2, the ASIC can be incorporated in practically any capsule endoscope, consuming only an idle-state power of 1.5mW

Operational experience and commissioning of the Belle II vertex detector

The construction of the new accelerator at the Super Flavor Factory in Tsukuba, Japan, has been finalized and the commissioning of its detector (Belle II) has started. This new e+e machine (SuperKEKB) will deliver an instantaneous luminosity of 8 1035 cm2s1, which is 40 times higher than the world record set by KEKB. In order to be able to fully exploit the increased number of events and provide high precision measurements of the decay vertex of the B meson systems in such a harsh environment, the Belle II detector will include a new 6 layer silicon vertex detector. Close to the beam pipe, 2 pixel and 4 double-sided strip detector layers will be installed. During its first data taking period in 2018, the inner volume of the Belle II detector was only partially equipped with the final vertex detector technologies. The remaining volume was covered with dedicated radiation monitors, collectively called BEAST II, in order to investigate the particle and synchrotron radiation backgrounds near the interaction point. In this note, the milestones of the commissioning of the Belle II vertex detector and BEAST II are reviewed and the detector performance and selected background measurements will be presented

Time resolution and radiation tolerance of depleted CMOS sensors

Depleted Monolithic Active Pixel Sensors (DMAPS), also known as depleted CMOS sensors, are extremely attractive for particle physics experiments. As the sensing diode and readout electronics can be integrated on the same silicon substrate, DMAPS remove the need for hybridization. This results in thin detectors with reduced production time and costs. To achieve high speed and high radiation tolerance, DMAPS are manufactured in High Voltage (HV) processes on High Resistivity (HR) wafers. Today's most performant DMAPS are 50 μm thin and have 50 μm x 50 μm cell size with integrated mixed analog and digital readout electronics, 11 ns time resolution and 5 x 1015 1 MeV neq/cm2 radiation tolerance. DMAPS in HR/HV-CMOS have been adopted as the sensor technology for the pixel tracker for the Mu3e experiment and are under consideration for the ATLAS detector Phase-II Upgrade. However, in spite of the major improvements demonstrated by DMAPS, further research to achieve even more performant sensors is needed to realize the full potential of these sensors to meet the most challenging requirements for particle physics experiments planned for the future. This article describes the state-of-the-art of DMAPS in terms of time resolution and radiation tolerance, and presents specific work done by the CERNRD50 collaboration to further develop the performance of these sensors

Active gating as a method to inhibit the crosstalk of Single Photon Avalanche Diodes in a shared well

This work presents low noise readout circuits for silicon pixel detectors based on Geiger mode avalanche photodiodes. Geiger mode avalanche photodiodes offer a high intrinsic gain as well as an excellent timing accuracy. In addition, they can be compatible with standard CMOS technologies. However, they suffer from a high intrinsic noise, which induces false counts indistinguishable from real events and represents an increase of the readout electronics area to store the false counts. We have developed new front-end electronic circuitry for Geiger mode avalanche photodiodes in a conventional 0.35 µm HV-CMOS technology based on a gated mode of operation that allows low noise operation. The performance of the pixel detector is triggered and synchronized with the particle beam thanks to the gated acquisition. The circuits allow low reverse bias overvoltage operation which also improves the noise figures. Experimental characterization of the fabricated front-end circuit is presented in this work

A Point-of-Care Device for Molecular Diagnosis Based on CMOS SPAD Detectors with Integrated Microfluidics

We describe the integration of techniques and technologies to develop a Point-of-Care for molecular diagnosis PoC-MD, based on a fluorescence lifetime measurement. Our PoC-MD is a low-cost, simple, fast, and easy-to-use general-purpose platform, aimed at carrying out fast diagnostics test through label detection of a variety of biomarkers. It is based on a 1-D array of 10 ultra-sensitive Single-Photon Avalanche Diode (SPAD) detectors made in a 0.18 μm High-Voltage Complementary Metal Oxide Semiconductor (HV-CMOS) technology. A custom microfluidic polydimethylsiloxane cartridge to insert the sample is straightforwardly positioned on top of the SPAD array without any alignment procedure with the SPAD array. Moreover, the proximity between the sample and the gate-operated SPAD sensor makes unnecessary any lens or optical filters to detect the fluorescence for long lifetime fluorescent dyes, such as quantum dots. Additionally, the use of a low-cost laser diode as pulsed excitation source and a Field-Programmable Gate Array (FPGA) to implement the control and processing electronics, makes the device flexible and easy to adapt to the target label molecule by only changing the laser diode. Using this device, reliable and sensitive real-time proof-of-concept fluorescence lifetime measurement of quantum dot QdotTM 605 streptavidin conjugate is demonstrated

Pràctiques de Disseny i Síntesi de Sistemes Digitals - Bus I2C

Aquest document serveix com una guia per a les sessions pràctiques de Disseny i Síntesi de Sistemes Digitals, específicament dissenyada per als alumnes del Grau d'Enginyeria Electrònica de Telecomunicació. Detalla el procés integral de disseny d'un sistema digital, oferint una orientació pas a pas en la creació d'un dispositiu mestre del bus I2C. El document abasta totes les etapes, des de la concepció inicial del disseny fins a la verificació rigorosa i la implementació final en una FPGA, amb l'objectiu específic d'interactuar de manera efectiva amb un sensor. Aquesta guia es presenta com una eina indispensable per a l'assoliment de competències pràctiques en l'àmbit de la síntesi digital

Laboratori de Disseny i Síntesi de Sistemes Digitals

Grau Enginyeria Electrònica de TelecomunicacióGuió del laboratori de l'assignatura Disseny i Síntesis de Sistemes Digitals

Millora de la implicació de l’alumne en Disseny i Síntesis de Sistemes Digitals fent ús d’eines d’avaluació continuada i debats en grup

Projecte: 2016PID-UB/013Durante los últimos 3 años se ha observado que el alumnado no tiene una base sólida para entender los conceptos que se introducen en la asignatura. Además, la actitud de los alumnos, en general, es de dejadez, no repasan conceptos para preparar la asignatura, no se preparan las prácticas de laboratorio y dejan de asistir a las clases presenciales. Dando como resultado una alta tasa de abandono, miedo a realizar la asignatura y malestar con el profesorado. Para resolver esta problemática, se aplica la innovación docente presentada en este artículo. Dicha innovación saca beneficio de estrategias docentes como la gamificación o el aprendizaje basado en problemas, usa herramientas virtuales para motivar el “e-learning” y la colaboración con el resto de estudiantes. Los resultados, hasta la fecha, son satisfactorios dado que reducen la tasa de abandono e incrementan el número de estudiantes que asimilan los conceptos introducidos en la asignatura.Programa d'Innovació i Millora de l'Aprenentatge - 2016PID-UB/01

Mejora de la implicación del alumnado en “Diseño y síntesis de sistemas digitales” usando e-learning colaborativo, gamificación y aprendizaje basado en problemas

[eng] During the last 3 years, it has been observed that the students do not have a solid base to understand the concepts that are introduced in the subject. In addition, the attitude of the students, in general, is negligence, do not review concepts to prepare the subject, do not prepare laboratory practices and stop attending class. This results in a high dropout rate, fear of doing the subject and discomfort with the teaching staff. To solve this problem, we apply the teaching innovation presented in this article. Such innovation takes advantage of teaching strategies such as gamification or problem-based learning, uses virtual tools to motivate e-learning and collaboration with other students. The results, to date, are satisfactory since they reduce the dropout rate and increase the number of students who assimilate the concepts introduced in the subje[spa] Durante los últimos 3 años se ha observado que el alumnado no tiene una base sólida para entender los conceptos que se introducen en la asignatura. Además, la actitud de los alumnos, en general, es de dejadez, no repasan conceptos para preparar la asignatura, no se preparan las prácticas de laboratorio y dejan de asistir a las clases presenciales. Dando como resultado una alta tasa de abandono, miedo a realizar la asignatura y malestar con el profesorado. Para resolver esta problemática, se aplica la innovación docente presentada en este artículo. Dicha innovación saca beneficio de estratégias docentes como la gamificación o el aprendizaje basado en problemas, usa herramientas virtuales para motivar el “e-learning” y la colaboración con el resto de estudiantes. Los resultados, hasta la fecha, son satisfactorios dado que reducen la tasa de abandono e incrementan el número de estudiantes que asimilan los conceptos introducidos en la asignatura.Este trabajo ha sido financiado por el “Programa de Millora I Innovació Docent” (PMID) y el grupo de innovación docente IDEES del Departamento de Ingenieria: Sección Electrónica, ambos perteneces a la Universitat de Barcelon

Readout electronics for low dark count pixel detectors based on geiger mode avalanche photodiodes fabricated in conventional CMOS technologies for future linear colliders

The high sensitivity and excellent timing accuracy of Geiger mode avalanche photodiodes makes them ideal sensors as pixel detectors for particle tracking in high energy physics experiments to be performed in future linear colliders. Nevertheless, it is well known that these sensors suffer from dark counts and afterpulsing noise, which induce false hits (indistinguishable from event detection) as well as an increase of the necessary area of the readout system. In this work, we present a comparison between APDs fabricated in a high voltage 0.35 µm and a high integration 0.13 µm commercially available CMOS technologies that has been performed to determine which of them best fits the particle collider requirements. In addition, a readout circuit that allows low noise operation is introduced. Experimental characterization of the proposed pixel is also presented in this work